Push updates...
1. Cleanup/Linting/Tweaks/Fixes/etc - Default Prettier config w/ 999 line length - Default eslint config "problems" list trimmed down 2. Fixed corrupt pointer cleanup by abc 3. Fixed `ip6po_rthdr` offset for PS5 by abc 4. Verified the number of blocking requests needed to be two by abc 5. Only run kernel exploit once by checking setuid by @JTAG7371 6. Kernel patches from pOOBs4 by @ChendoChap (Ported for 8.00-9.60) 7. Payload loader from pOOBs4 by @ChendoChap 8. Restore syscall 661 (`sys_aio_submit()`) after patching by @janisslsm 9. Add `PROT_READ`, `PROT_WRITE`, `PROT_EXEC` constants for payload loader by @janisslsm The ONLY things that should need changes are the `/rop/ps4/*.mjs` files (850, 900, and 950). Firmware 8.00 appears to be stable/have a good success rate now.
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@@ -60,8 +60,20 @@ void do_patch(void) {
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disable_cr0_wp();
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// patch amd64_syscall() to allow calling syscalls everywhere
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// ChendoChap's patches from pOOBs4 ///////////////////////////////////////
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// Initial patches
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write16(kbase, 0x624ae4, 0x9090); // veriPatch
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write8(kbase, 0xacd, 0xeb); // bcopy
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write8(kbase, 0x201c0d, 0xeb); // bzero
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write8(kbase, 0x201c51, 0xeb); // pagezero
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write8(kbase, 0x201ccd, 0xeb); // memcpy
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write8(kbase, 0x201d11, 0xeb); // pagecopy
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write8(kbase, 0x201ebd, 0xeb); // copyin
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write8(kbase, 0x20236d, 0xeb); // copyinstr
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write8(kbase, 0x20243d, 0xeb); // copystr
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// patch amd64_syscall() to allow calling syscalls everywhere
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// struct syscall_args sa; // initialized already
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// u64 code = get_u64_at_user_address(td->tf_frame-tf_rip);
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// int is_invalid_syscall = 0
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@@ -95,19 +107,16 @@ void do_patch(void) {
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// call qword [rax + 8] ; error = (sa->callp->sy_call)(td, sa->args)
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//
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// sy_call() is the function that will execute the requested syscall.
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write16(kbase, 0x4b5, 0x9090);
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write16(kbase, 0x4b9, 0x9090);
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write8(kbase, 0x4c2, 0xeb);
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write16(kbase, 0x4b9, 0x9090);
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write16(kbase, 0x4b5, 0x9090);
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// patch sys_mmap() to allow rwx mappings
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// patch maximum cpu mem protection: 0x33 -> 0x37
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// the ps4 added custom protections for their gpu memory accesses
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// GPU X: 0x8 R: 0x10 W: 0x20
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// that's why you see other bits set
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// ref: https://cturt.github.io/ps4-2.html
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write8(kbase, 0x122d7a, 0x37);
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write8(kbase, 0x122d7d, 0x37);
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// patch sys_setuid() to allow freely changing the effective user ID
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// ; PRIV_CRED_SETUID = 50
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// call priv_check_cred(oldcred, PRIV_CRED_SETUID, 0)
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// test eax, eax
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// je ... ; patch je to jmp
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write8(kbase, 0x1fa536, 0xeb);
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// patch vm_map_protect() (called by sys_mprotect()) to allow rwx mappings
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//
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@@ -119,8 +128,10 @@ void do_patch(void) {
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// }
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write32(kbase, 0x196d3d, 0);
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// patch sys_dynlib_dlsym() to allow dynamic symbol resolution everywhere
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// TODO: Description of this patch. "prx"
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write16(kbase, 0x19f724, 0xe990);
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// patch sys_dynlib_dlsym() to allow dynamic symbol resolution everywhere
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// call ...
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// mov r14, qword [rbp - 0xad0]
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// cmp eax, 0x4000000
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@@ -142,13 +153,14 @@ void do_patch(void) {
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// ...
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write32(kbase, 0x11960, 0xc3c03148);
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// patch sys_setuid() to allow freely changing the effective user ID
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// ; PRIV_CRED_SETUID = 50
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// call priv_check_cred(oldcred, PRIV_CRED_SETUID, 0)
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// test eax, eax
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// je ... ; patch je to jmp
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write8(kbase, 0x1fa536, 0xeb);
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// patch sys_mmap() to allow rwx mappings
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// patch maximum cpu mem protection: 0x33 -> 0x37
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// the ps4 added custom protections for their gpu memory accesses
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// GPU X: 0x8 R: 0x10 W: 0x20
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// that's why you see other bits set
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// ref: https://cturt.github.io/ps4-2.html
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write8(kbase, 0x122d7a, 0x37);
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write8(kbase, 0x122d7d, 0x37);
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// overwrite the entry of syscall 11 (unimplemented) in sysent
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//
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@@ -164,15 +176,12 @@ void do_patch(void) {
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// int sys_kexec(struct thread td, struct args *uap) {
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// asm("jmp qword ptr [rsi]");
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// }
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// sysent[11]
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const size_t offset_sysent_11 = 0x10f9500;
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// .sy_narg = 6
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write32(kbase, offset_sysent_11, 6);
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// .sy_narg = 2
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write32(kbase, 0x10f9500, 2);
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// .sy_call = gadgets['jmp qword ptr [rsi]']
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write64(kbase, offset_sysent_11 + 8, kbase + 0x15a6d);
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write64(kbase, 0x10f9500 + 8, kbase + 0x15a6d);
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// .sy_thrcnt = SY_THR_STATIC
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write32(kbase, offset_sysent_11 + 0x2c, 1);
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write32(kbase, 0x10f9500 + 0x2c, 1);
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enable_cr0_wp();
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}
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